1. Field of the Invention
This invention relates to a semiconductor device with a MOS structure, and more particularly to a structure of connecting wires to each other and a manufacturing method thereof.
2. Description of the Related Art
With the recent remarkable advances in very-large-scale integration technology for semiconductor devices including ICs and LSIs, circuit patterns and connecting wires are getting finer and multilevel structures of interconnections are now more commonplace. Particularly, in MOS transistors, their gate electrodes are connected via an interlayer insulating film to aluminium (Al) wires or refractory metal wires formed in the overlying layer. These wires are further electrically connected via another interlayer insulating film just above them to several wires in still another overlying layer.
FIGS. 8 and 9 show conventional semiconductor devices. In FIG. 8, on the main surface of a silicon semiconductor substrate 1, a field oxide film 2 is formed of, for example, an SiO.sub.2 film. In an area of the surface where the field oxide film 2 is not formed, a well area 11 such as a p well is formed. On the well area 11, a gate oxide film 3 is formed of, for example, a thin silicon oxide film. On the gate oxide film 3, the gate electrode 4 of a MOS transistor is formed of, for example, polysilicon. The gate electrode 4 extends over the field oxide film 2. The gate electrode 4 and field oxide film 2 are covered with a first insulating film 5 serving as an interlayer insulating film.
The surface of the first insulating film 5 is flattened. On the flattened surface, patterned aluminium wires of a first layer (hereinafter, referred to as the first Al wires) 61, 62 are formed. The first Al wire 61 is connected to the gate electrode 4 via a contact hole 51 made in the first insulating film 5. The first Al wires 61, 62 are covered with a second insulating film 7. An SiO.sub.2 film formed by, for example, plasma CVD techniques is used as the first and second insulating films 5, 7. The second insulating film 7 is flattened, and a photoresist 8 is applied to the flattened film 7. The photoresist 8 is exposed and developed to make an opening in the photoresist 8 to expose the second insulating film 7.
Using the patterned photoresist 8 as a mask, the second insulating film 7 is etched by RIE (Reactive Ion Etching) techniques to make openings 71, 72 in the second insulating film 7 to expose the first Al wires 61, 62. The first Al wire 61 carrying a large current is provided with the opening 71 whose cross-sectional area is large enough for the current, and the second Al wire 62 carrying a small current is provided with the opening 72 whose cross-sectional area is small. Then, the photoresist 8 is removed and the surface of the second insulating film 7 is flattened. On the second insulating film 7 and inside the openings 71, 72, aluminium wires of a second layer (hereinafter, referred to as the second Al wires) 91, 92 are formed as shown in FIG. 9. When etching is effected by the RIE technique, the first Al wires 61, 62 are also somewhat etched by the RIE. Although there is not a large effect because of the slow etching speed, the surface portions corresponding to the openings 71, 72 of the wires are lower than the other surface portions.
As described above, etching is important techniques for manufacturing miniaturized semiconductor devices. Forming a desired pattern in a polycrystal silicon film or an SiO.sub.2 film requires high-accuracy etching. In addition to conventional wet etching in solution, plasma etching by means of discharge in gases including halogen and oxygen and dry etching such as RIE have recently been used. In particular, RIE is an important technique in manufacturing high-density semiconductor devices, because the RIE technique enables high-accuracy etching and allows simplification of processes.
To etch an SiO.sub.2 film, gases of the fluorocarbon family are used, for example. When the second insulating film 7 is etched by RIE techniques, ions used for etching are charged on the first Al wire 61 corresponding to the large opening 71, causing the potential difference between the top and bottom of the gate oxide film 3. The potential difference causes charges to be trapped in the gate oxide film 3, resulting in fluctuations in the threshold voltage Vth of the MOS transistor. When the potential difference is great, the gate oxide film 3 is destroyed, which will introduce a serious problem to the processing of the semiconductor device and its reliability.
To overcome this problem, it has been a conventional practice to connect a protective element such as a diode to the first Al wire. The protective element prevents charges generated by RIE from being trapped in the gate oxide film. When the effect of charges is great, the protective element must be large accordingly. Thus, the protective element hinders semiconductor devices from being more highly integrated or miniaturized. The phenomenon that charges generated by RIE destroy the gate electrode becomes more noticeable as the semiconductor device is miniaturized more. In particular, when the thickness of the gate oxide film is less than 45 to 50 nm, even a small amount of charges will destroy the gate oxide film. Therefore, the phenomenon is a serious problem.